1. Field of the Invention
The present invention relates to apparatus and a method related to a test structure for capacitance-voltage (Cxe2x88x92V) measurements for very thin oxides.
2. Description of the Related Art
Oxides as thin as 13-15 angstroms have been used as gate dielectrics to fabricate sub-100-nm polysilicon-gated CMOS devices. See, for example, G. C.-F. Yeap et al., Sub-100-nm nMOSFET""s with direct tunneling thermal, nitrous, and nitric oxides,xe2x80x9d in Proc. 56th Annu. Dev. Res. Conf. (DRC), Charlottesville, Va. 1998, pp. 10-11; G. Timp et al., xe2x80x9cLow leakage, ultra-thin gate oxides for extremely high performance sub-100-nm nMOSFET""s ,xe2x80x9d in IEDM Tech. Dig., 1994, pp. 593-596; D. A. Buchanan and S.-H. Lo, xe2x80x9cReliability and integration of ultra-thin gate dielectrics for advanced CMOS,xe2x80x9d in Microelectron. Eng., vol. 36, pp. 13-20, 1997; and J. Hauser and K. Ahmed, xe2x80x9cCharacterization of ultrathin oxides using electrical Cxe2x88x92V and Ixe2x88x92V measurements,xe2x80x9d in National Institutes of Standards and Technology, Gaithersburg, Md., Mar. 23-27, 1998. Characterization of sub-0.1 xcexcm CMOS devices requires accurate determination of the device material and physical parameters, such as oxide thickness tox, oxide charges Q,f, surface doping in the substrate (Nsub) and polysilicon-gate doping (Npoly) densities, and interface state density. Although high frequency (HF) Cxe2x88x92V, measured on MOS capacitor structures, can be used for estimating tox, Q,f and Nsub, it is necessary to use MOSFET structures to obtain the low-frequency-like (LF) Cxe2x88x92V curve in strong inversion to estimate Npoly, especially for sub-30 xc3x85 oxides. With a MOSFET, the inversion layer charge is maintained by the minority carriers supplied by the source and drain junctions. To avoid distortion of the Cxe2x88x92V curve due to channel charging effects, it is necessary to use MOSFET structures with proper channel length L, and measurement frequency f, in order to satisfy the condition: 2xcfx80fxc3x97xcfx84gc less than  less than 1, where, xcfx84gcxe2x88x9d(L2xc2x7tox)xe2x88x921 is the channel time constant. See P.-M. D. Chow and K.-L. Wang, xe2x80x9cA new AC technique for accurate determination of channel charge and mobility in very thin gate MOSFET""s ,xe2x80x9d in IEEE Trans. Electron Devices, vol. ED-33, pp. 1299, September 1986; U. Lieneweg, xe2x80x9cFrequency response of charge transfer in MOS inversion layers,xe2x80x9d in Solid-State Electron., vol. 23, pp. 577-583, 1980. This condition sets an upper limit on L for a given frequency f. In addition, accuracy requirements imposes a lower limit on L, in order to minimize gate overlap capacitance parasitic effects, and a lower limit exists on the measurement frequency for any capacitance meter to accurately separate capacitive and conductive components of the measured impedance, especially for sub-20 xc3x85 devices.
Anomalous dependence on Cxe2x88x92V characteristics on test structure geometry for sub-15 xc3x85 oxides have been reported. See Bayomi et al., xe2x80x9cProcess, characterization and integrity issues for 15 xc3x85 gate oxides,xe2x80x9d in Proc. 1998 Hewlett-Packard Silicon Technology Conf., Portland, Oreg., Mar. 31-Apr. 3, 1998, pp. 33-38. It was reported that the capacitance measured on large area capacitor or transistor structures show large attenuation in both strong inversion and accumulation bias regimes. The capacitance attenuation was found to increase with increasing the gate area in both bias regimes. A model with distributed gate sheet resistance and bias-dependent tunneling conductance was proposed and used to explain the observed experimental data. However, although the polysilicon gate sheet-resistance may be important in accumulation, the present inventors have determined that the channel resistance will be dominant in strong inversion, especially for MOSFETs with silicided polysilicon gates. This can be seen from the dependence of the strong inversion capacitance roll-off on the channel length, as will be explained in more detail below.
The invention provides a method and apparatus for test structures for capacitance-voltage measurements for very thin oxides.
A test structure may include a first MOSFET having a channel length less than a predetermined channel length, and a second MOSFET having a channel length less than the predetermined channel length. The first and second MOSFETS are connected in parallel. Device parameters are capable of being extracted from the MOSFET test structure. Effects due to tunneling currents and channel dimensions are considered in determining a terminal capacitance of the MOSFET test structure.
A MOSFET test structure method includes modeling a first MOSFET having a channel length less than a predetermined channel length; and modeling a second MOSFET having a channel length less than the predetermined channel length. The method also includes connecting the first and second MOSFETS in parallel. At least one device parameter is capable of being extracted utilizing the MOSFET test structure.